RISC versus CISC

The old discussion about RISC versus CISC suddenly became on the agenda again after my article about AVR to ARM.

Anders from IAR systems and a few others have contacted me to say that to call ARM a CISC was not correct. There is no doubt about that, ARM is a RISC, not a CISC processor. Advanced Risc Machines develops RISC processors.

In my article I referred to the beginning of the ARM and the beginning of AVR. The first ARM device we used was one of the first ARM 7 based architectures. This architecture had a Von Neumann bus structure, which means that there is one shared bus for program code, data and I/O. Most processor architects would say that RISC processors should have a Harvard architecture where there are separate busses for the different memories. This was implemented in the ARM 9 and it almost doubled the performance of the core. There are also CISC processors utilizing the Harvard architecture so I guess the border between CISC and RISC will never be 100% clear. However, my previous article should have been written differently. My bad.

Many people think that RISC means reduced number of instructions. Reduced in the RISC term refers to the complexity of the instructions. A RISC processor has an instruction set where every instruction is executed mostly in one clock cycle and hereby becomes very efficient in terms of execution speed. However, this requires different hardware support because it can be viewed more like “parallel processing” versus a CISC that has complex instructions and some instructions have small state machines that use multiple. For example the multiply instruction take one clock cycle in AVR and 48 in the original C51 core.

When we designed the AVR we actually added a lot of instructions to avoid having every instruction too flexible. By adding more instruction we could keep them simple and very efficient. By working with IAR systems on the C-compiler we also ended up with a very code efficient machine.

For embedded processors used in control application it is also very important to have a processor that can handle single bits in registers, memory and I/O very efficient. It is interesting to note that the C51 designed by Intel in 1980 had bit level “boolean logic” operations. These operations can be used on internal registers and a dedicated portion of the RAM memory. A similar functionality was also implemented in the AVR to make it extremely efficient for control applications. The original AVR architecture before it became Atmel was designed to do very efficient descrambling of bit streams sent to digital TV sets.

The next level of efficiency for embedded application is what the I/O Communicates without the CPU involved. This was implemented in the XMEGA AVR and an even more efficient system is implemented in the EFM32 from Energy Micro. The EFM32 has a so-called Reflex system where peripherals can be programmed to wake up each other and pass data along as needed. This is mostly implemented to utilize the low power modes of the EFM32, and will also improve the performance of the system.

One response to “RISC versus CISC

  1. Pingback: From AVR to ARM: The shift to 32-bit MCUs in the embedded world | Official Blog of Energy Micro

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